Augmenting Loop Tiling with Data Alignment for Improved Cache Performance

  • Authors:

  • Preeti Ranjan Panda;Hiroshi Nakamura;Nikil D. Dutt;Alexandru Nicolau

  • Affiliations:

  • Synopsys, Inc., Mountain View, CA;Univ. of Tokyo, Tokyo, Japan;Univ. of California at Irvine, Irvine;Univ. of California at Irvine, Irvine

  • Venue:
  • IEEE Transactions on Computers - Special issue on cache memory and related problems
  • Year:
  • 1999

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Abstract

Loop blocking (tiling) is a well-known compiler optimization that helps improve cache performance by dividing the loop iteration space into smaller blocks (tiles); reuse of array elements within each tile is maximized by ensuring that the working set for the tile fits into the data cache. Padding is a data alignment technique that involves the insertion of dummy elements into a data structure for improving cache performance. In this work, we present DAT, a technique that augments loop tiling with data alignment, achieving improved efficiency (by ensuring that the cache is never under-utilized) as well as improved flexibility (by eliminating self-interference cache conflicts independent of the tile size). This results in a more stable and better cache performance than existing approaches, in addition to maximizing cache utilization, eliminating self-interference, and minimizing cross-interference conflicts. Further, while all previous efforts are targetted at programs characterized by the reuse of a single array, we also address the issue of minimizing conflict misses when several tiled arrays are involved. To validate our technique, we ran extensive experiments using both simulations as well as actual measurements on SUN Sparc5 and Sparc10 workstations. The results on benchmarks exhibiting varying memory access patterns demonstrate the effectiveness of our technique through consistently high hit ratios and improved performance across varying problem sizes.