Performance Analysis of Cache Memories
Journal of the ACM (JACM)
ACM Computing Surveys (CSUR)
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Organization and analysis of a gracefully-degrading interleaved memory system
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Multiprocessor cache design considerations
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
Analysis of memory referencing behavior for design of local memories
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ACM Transactions on Computer Systems (TOCS)
Design and Analysis of a Gracefully Degrading Interleaved Memory System
IEEE Transactions on Computers
An empirical study of the CRAY Y-MP processor using the Perfect club benchmarks
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
The effectiveness of caches for vector processors
ICS '94 Proceedings of the 8th international conference on Supercomputing
Using cache memory to reduce processor-memory traffic
25 years of the international symposia on Computer architecture (selected papers)
PIPE: a VLSI decoupled architecture
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Transforming loops to recursion for multi-level memory hierarchies
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
IEEE Transactions on Computers
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
The use of static column ram as a memory hierarchy
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Cache hit ratios with geometric task switch intervals
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Design and Optimization of Large Size and Low Overhead Off-Chip Caches
IEEE Transactions on Computers
Synapse tightly coupled multiprocessors: a new approach to solve old problems
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
An efficient simulation algorithm for cache of random replacement policy
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
| Hi-index | 0.01 |
Instruction caches are analyzed both theoretically and experimentally. The theoretical analysis begins with a new model for cache referencing behavior—the loop model. This model is used to study cache organizations and replacement policies. It is concluded theoretically that random replacement is better than LRU and FIFO, and that under certain circumstances, a direct-mapped or set associative cache may perform better than a full associative cache organization. Experimental results using instruction trace data are then given. The experimental results are shown to support the theoretical conclusions.