The use of static column ram as a memory hierarchy

Authors:
James R. Goodman;Men-chow Chiang
Affiliations:
Department of Computer Sciences, University of Wisconsin-Madison, Madison, WI;Department of Computer Sciences, University of Wisconsin-Madison, Madison, WI
Venue:
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Year:
1984

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Abstract

The Static Column RAM devices recently introduced offer the potential for implementing a direct-mapped cache on-chip with only a small increase in complexity over that needed for a conventional dynamic RAM memory system. Trace-driven simulation shows that such a cache can only be marginally effective if used in the obvious way. However it can be effective in satisfying the requests from a processor containing an on-chip cache. The SCRAM cache is more effective if the processor cache handles both instructions and data.