Organization and analysis of a gracefully-degrading interleaved memory system

Authors:
K. Cheung;G. Sohi;K. Saluja;D. Pradhan
Affiliations:
University of Wisconsin, Madison, WI;University of Wisconsin, Madison, WI;University of Wisconsin, Madison, WI;University of Massachusetts, Amherst, MA
Venue:
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Year:
1987

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Abstract

A hardware mechanism has been proposed to reconfigure an interleaved memory system. The reconfiguration scheme is such that, at any instant all fault-free memory banks in the memory system are utilized in interleaved manner. A performance metric is defined which takes into account the bandwidth and the page-fault rate in an interleaved memory system. The reconfiguration scheme proposed in this paper is analyzed for a number of distinct programs using the performance metric defined in the paper. It is shown that the system performance degrades slowly, as the number of faulty banks increase, in a memory system using the proposed reconfiguration scheme.