Optimal reconfiguration strategy for a degradable multimodule computing system
Journal of the ACM (JACM)
Organization and analysis of a gracefully-degrading interleaved memory system
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
RAID: high-performance, reliable secondary storage
ACM Computing Surveys (CSUR)
Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Inexact agreement: accuracy, precision, and graceful degradation
Proceedings of the fourth annual ACM symposium on Principles of distributed computing
A prioritized real-time wireless call degradation framework for optimal call mix selection
Mobile Networks and Applications - Analysis and Design of Multi-Service Wireless Networks
Specifying Graceful Degradation
IEEE Transactions on Parallel and Distributed Systems
A Dynamic Reconfiguration Service for CORBA
CDS '98 Proceedings of the International Conference on Configurable Distributed Systems
A design study of a shared resource computing system
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Diagnostic And Computational Reconfiguration In Multiprocessor Systems
ACM '78 Proceedings of the 1978 annual conference
Improving System Dependability with Functional Alternatives
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Basic Concepts and Taxonomy of Dependable and Secure Computing
IEEE Transactions on Dependable and Secure Computing
Surviving Errors in Component-Based Software
EUROMICRO '05 Proceedings of the 31st EUROMICRO Conference on Software Engineering and Advanced Applications
Patterns for Fault Tolerant Software
Patterns for Fault Tolerant Software
Robust image transmission over CDMA channels
IEEE Transactions on Consumer Electronics
HCII'11 Proceedings of the 14th international conference on Human-computer interaction: design and development approaches - Volume Part I
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Graceful degradation describes the smooth change of some distinct system feature to a lower state as a response to an event that prevents the system from exhibiting that feature in its full state. Such system behavior has appeared in a variety of domains from image processing and telecommunications to shared memory multiprocessors and multi-modular memory systems. In each domain, graceful degradation has targeted a different system feature, e.g. image quality, voice quality, computational capacity, memory access throughput, etc. However, irrespectively of the system feature that has been gracefully degraded, the basic concepts behind the mechanisms responsible for this behavior have been similar. This paper presents a design pattern that captures the general idea behind graceful degradation, plus three more patterns that describe how to smoothly reach a lower system state under different circumstances.