Dynamic RAM for on-chip instruction caches

Authors:
Jordi Cortadella;Teodor Jové
Affiliations:
Departament d'Arquitectura de Computadors, Universistat Politècnica de Catalunya, Facultat d'Informàtica, Pau Gargallo, 5, 08028 - BARCELONA (Spain);Departament d'Arquitectura de Computadors, Universistat Politècnica de Catalunya, Facultat d'Informàtica, Pau Gargallo, 5, 08028 - BARCELONA (Spain)
Venue:
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
Year:
1988

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An Introduction to GaAs Microprocessor Architecture for VLSI

Computer
VLSI engineering

VLSI engineering
Cache Memories

ACM Computing Surveys (CSUR)
Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers)

Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers)

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Abstract

On-chip memories are commonly used to reduce the external communication bandwidth of current microprocessors. Implementations with static RAM allow simple synchronization structures. The use of dynamic RAM results in an important area saving but complicates the processor control due to the refresh requirements. In this paper, a simple design approach, based on the use of dynamic RAM, is introduced for implementing on-chip instruction caches without complicating the processor control.