A Study of Channeled DRAM Memory Architectures

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ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Year:
2000

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Abstract

Channeled DRAM features small on-chip buffers called channels that are placed in front of the DRAM core. In this study, various techniques to efficiently control the channels were investigated. Different techniques of caching and prefetching were adapted to the unique features of Channeled DRAM. A memory simulation library extended an existing execution-driven processor simulator and three benchmarks were run on four different memory system configurations of this simulator to evaluate the performance of the different control strategies. As a result, using Channeled DRAM as replacement for conventional SDRAM improves the memory system performance by reducing the average access latency up to 50%.