Design and performance of special purpose hardware for time warp

  • Authors:
  • R. M. Fujimoto;J.-J. Tsai;G. Gopalakrishnan

  • Affiliations:
  • Univ. of Utah, Salt Lake City;Univ. of Utah, Salt Lake City;Univ. of Utah, Salt Lake City

  • Venue:
  • ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
  • Year:
  • 1988

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Abstract

A special purpose simulation engine based on the Time Warp mechanism is proposed to attack large-scale discrete event simulation problems. A key component of this engine is the rollback chip, a hardware component that efficiently implements state saving and rollback functions in Time Warp. The algorithms implemented by the rollback chip are described, as well as mechanisms that allow efficient implementation. Results of simulation studies are presented that show that the rollback chip can virtually eliminate the state saving overhead that plagues current software implementations of Time Warp.