ACM Transactions on Computer Systems (TOCS)
ACM Transactions on Computer Systems (TOCS)
Analysis of cache invalidation patterns in multiprocessors
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
The Stack Growth Function: Cache Line Reference Models
IEEE Transactions on Computers
IEEE Transactions on Computers
Synthetic Traces for Trace-Driven Simulation of Cache Memories
IEEE Transactions on Computers
Cache evaluation and the impact of workload choice
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Cold-start vs. warm-start miss ratios
Communications of the ACM
The working set model for program behavior
Communications of the ACM
Two economical directory schemes for large-scale cache coherent multiprocessors
ACM SIGARCH Computer Architecture News
Analysis of cache replacement-algorithms
Analysis of cache replacement-algorithms
An inter-reference gap model for temporal locality in program behavior
Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
An analytical model of the working-set sizes in decision-support systems
Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
The effect of seance communication on multiprocessing systems
ACM Transactions on Computer Systems (TOCS)
Establishing a tight bound on task interference in embedded system instruction caches
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Timekeeping in the memory system: predicting and optimizing memory behavior
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
| Hi-index | 14.98 |
An analytical model that predicts the fraction of live and dead lines present in a cache memory in a multitasking environment is presented. The model is two-fold. The first portion evaluates the number of live lines created in a fully associative cache during the execution of a process. The second portion models the interaction of two processes that share a cache and run in an interleaved fashion. The model admits direct-mapped, set-associative, and fully associative cache architectures. The complete model assumes a hyperbolic (or fractal) model of program behavior. It predicts the variations of the total number of lines (footprint) as well as the number of live lines held by a process in the various caches as a function of the number of cache accesses. The accuracy of the model is validated through trace driven simulations.