A class of compatible cache consistency protocols and their support by the IEEE futurebus
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
On the inclusion properties for multi-level cache hierarchies
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ACM Transactions on Computer Systems (TOCS)
IEEE Transactions on Computers
SIGMETRICS '91 Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment
IEEE Transactions on Computers
Screening, predicting, and computer experiments
Technometrics
Cache miss equations: an analytical representation of cache misses
ICS '97 Proceedings of the 11th international conference on Supercomputing
Memory system characterization of commercial workloads
Proceedings of the 25th annual international symposium on Computer architecture
Analytic evaluation of shared-memory systems with ILP processors
Proceedings of the 25th annual international symposium on Computer architecture
AMVA techniques for high service time variability
Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
ACM Computing Surveys (CSUR)
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes
IEEE Transactions on Computers
A performance methodology for commercial servers
IBM Journal of Research and Development
IBM Journal of Research and Development
A case study in top-down performance estimation for a large-scale parallel application
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Comprehensive multivariate extrapolation modeling of multiprocessor cache miss rates
ACM Transactions on Computer Systems (TOCS)
Determining output uncertainty of computer system models
Performance Evaluation
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Defining relevant distances between server workloads
Performance Evaluation
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
Amdahl's law in the era of process variation
International Journal of High Performance Systems Architecture
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This article presents a technique for taking a sparse set of cache simulation data and fitting a multivariate model to fill in the missing points over a broad region of cache configurations. We extend previous work by its applicability to multiple miss rate components and its ability to model a wide range of cache parameters, including size, associativity and sharing. Miss rate models are useful for broad design exploration in which many cache configurations cannot be simulated directly due to limitations of trace collection setups or available resources. We show the effectiveness of the technique by applying it to two commercial workloads and presenting miss rate data for a broad design space with cache size, associativity, sharing and number of processors as variables. The fitted data match the simulation data very well. The various curves show how a miss rate model is useful for not only estimating the performance of specific configurations, but also for providing insight into miss rate trends. Furthermore, this modeling methodology is robust in the presence of corrupted simulation data and variations in simulation data from multiple sources.