Stride directed prefetching in scalar processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Prefetching Using Markov Predictors
IEEE Transactions on Computers - Special issue on cache memory and related problems
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
ACM Computing Surveys (CSUR)
Improving Data Prefetching Efficacy in Multimedia Applications
Multimedia Tools and Applications
General-Purpose Processor Huffman Encoding Extension
ITCC '00 Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00)
Hierarchical Partitioning for Piecewise Linear Algorithms
PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
A Novel System-on-Chip Architecture for Efficient Image Processing
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
Exploiting Cache in Multimedia
ICMCS '99 Proceedings of the IEEE International Conference on Multimedia Computing and Systems - Volume 2
A dynamically tunable memory hierarchy
IEEE Transactions on Computers
A platform for high level synthesis of memory-intensive image processing algorithms
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
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In this paper, we propose a low-cost n-dimensional cache (nD-Cache) architecture for FPGA-Based image and signal processing Systems On Chip (SoCs). The architecture allows efficient access to structured data such as in 2D or 3D images. We developed a theoretical model for our architecture. It gives a methodology to define the cache’s practical implementation based on the application and system parameters. Complexity and performance for selected image processing algorithms like jumping snake and 2D Back-Projection are measured and compared to classical solutions like associative caches. The architecture is shown to be efficient for tracking algorithm applications by exploiting spacial and temporal locality. Numerical results indicate that 50% improvement in run-time performance can be achieved.