A Novel System-on-Chip Architecture for Efficient Image Processing

Authors:
V. Mariatos;K. D. Adaos;G. P. Alexiou
Affiliations:
-;-;-
Venue:
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
Year:
2008

Citing 0
Cited 1

Efficient Data Access Management for FPGA-Based Image Processing SoCs

RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping

Quantified Score

Hi-index	0.00

Visualization

Abstract

Complex image processing algorithms, when implemented on chip, require a significant amount of memory. Communication between the processing elements of an image processing system consumes most of the bandwidth of the system bus. This paper presents a novel architecture for a system on chip targeting image processing applications. Main focus is placed on optimizing the communication overhead between the image processing elements. Evaluation of this architecture is made in a custom FPGA platform and in ASIC implementation.