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IEEE Transactions on Computers
Efficient (stack) algorithms for analysis of write-back and sector memories
ACM Transactions on Computer Systems (TOCS)
ACM Transactions on Computer Systems (TOCS)
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
High-performance computer architecture (2nd ed.)
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Computer - Special issue on experimental research in computer architecture
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ACM Computing Surveys (CSUR)
A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches
IEEE Transactions on Computers
IEEE Transactions on Computers
Efficient simulation of trace samples on parallel machines
Parallel Computing
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ACM SIGMETRICS Performance Evaluation Review - Special issue on tools for computer architecture research
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LCR '04 Proceedings of the 7th workshop on Workshop on languages, compilers, and run-time support for scalable systems
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Journal of Systems Architecture: the EUROMICRO Journal
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations
IEEE Transactions on Computers
Yet shorter warmup by combining no-state-loss and MRRL for sampled LRU cache simulation
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ANSS '06 Proceedings of the 39th annual Symposium on Simulation
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Proceedings of the 2007 ACM symposium on Applied computing
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Transactions on High-Performance Embedded Architectures and Compilers II
Branch history matching: branch predictor warmup for sampled simulation
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
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ICCS'03 Proceedings of the 2003 international conference on Computational science: PartIII
Efficient sampling startup for sampled processor simulation
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
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Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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ACM Computing Surveys (CSUR)
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The design of the memory hierarchy is crucial to the performance of high performance computer systems. The incorporation of multiple levels of caches into the memory hierarchy is known to increase the performance of high end machines, but the development of architectural prototypes of various memory hierarchy designs is costly and time consuming. In this paper, we will describe a single pass method used in combination with trace sampling techniques to produce a fast and accurate approach for simulating multiple sizes of caches simultaneously.