High-performance computer architecture
High-performance computer architecture
Tradeoffs in two-level on-chip caching
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
NStrace: a bus-driven instruction trace tool for PowerPC microprocessors
IBM Journal of Research and Development - Special issue: performance analysis and its impact on design
The capture, characterization, and performance analysis of Macintosh traces
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
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Address traces are acquired typically in order to evaluate different cache organizations and memory hierarchy designs. Address traces have other uses, however. For example, traces can provide information about patterns of different types of memory accesses (e.g. reads versus writes). If the trace data includes time stamps, bursts of accesses can be detected and analyzed. This paper describes a series of studies performed on a PowerPC based Macintosh computer to examine memory transaction behavior using time stamped address traces. The measurement setups and workloads are described, along with a description of the results obtained.