Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
The influence of parallel decomposition strategies on the performance of multiprocessor systems
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Experience Using Multiprocessor Systems—A Status Report
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Concepts and Notations for Concurrent Programming
ACM Computing Surveys (CSUR)
Microcomputer Busses and Links
Microcomputer Busses and Links
Size, power, and speed (Keynote Address)
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Lockup-free instruction fetch/prefetch cache organization
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Performance measurements on a commercial multiprocessor running parallel code
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor
IEEE Transactions on Computers
Combining produce and consume operations in a pipelined shared memory multiprocessor
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Quick and easy cache performance analysis
ACM SIGARCH Computer Architecture News
The Run-Time Efficiency of Parallel Asynchronous Algorithms
IEEE Transactions on Computers
A scalable snoopy coherence scheme on distributed shared-memory multiprocessors
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Bounding the gain of changing the number of memory modules in shared memory multiprocessors
Nordic Journal of Computing
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
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The performance of cache-based multiprocessors for general-purpose computing and for multitasking is analyzed with simple throughput models. A private cache is associated with each processor, and multiple buses connect the processors to the shared, interleaved memory. Simple models based on dynamic instruction mix statistics are introduced to evaluate upper bounds on the throughput when independent tasks are run on each processor. With these models, one can obtain a first estimate of the MIPS (millions of instructions per second) rate of a multiprocessor.