Computer architecture and organization; (2nd ed.)
Computer architecture and organization; (2nd ed.)
Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses
IEEE Transactions on Computers
Operating system concepts (3rd ed.)
Operating system concepts (3rd ed.)
Efficient architectures for data access in a shared memory hierarchy
Journal of Parallel and Distributed Computing
Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model
IEEE Transactions on Computers
Mathematica: a system for doing mathematics by computer (2nd ed.)
Mathematica: a system for doing mathematics by computer (2nd ed.)
Contention in shared memory algorithms
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
An optimal upper bound on the minimal completion time in distributed supercomputing
ICS '94 Proceedings of the 8th international conference on Supercomputing
An Optimal Execution Time Estimate of Static versus Dynamic Allocation in Multiprocessor Systems
SIAM Journal on Computing
Conflict-Free Access for Streams in Multimodule Memories
IEEE Transactions on Computers
Multiskewing-A Novel Technique for Optimal Parallel Memory Access
IEEE Transactions on Parallel and Distributed Systems
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We consider a multiprocessor, with p processors and m memory modules. If more than one processor want to access a memory module simultaneously, these accesses will be serialized due to memory contention. The completion time of a program executing on this system is thus affected by the way addresses are mapped onto memory modules, and finding a mapping which results in minimal completion time is NP-hard.If we change the number of memory modules from m to m', while keeping the number processors constant, we will generally change the minimal completion time. The gain of changing the number of memory modules from m to m' for a certain program is defined as the ratio between the minimal completion times, using m and m' modules respectively.Here, we present an optimal upper bound on the maximum gain of changing the number of memory modules, as a function of m, m' and p, including the case when m' is infinitely large. The bound is obtained by investigating a mathematical formulation. The mathematical tools involved are essentially elementary combinatorics. The formula for calculating the bound is mathematically complicated but can be rapidly computed for reasonable m, m' and p.This bound makes it possible to do price-performance trade-offs and to compare any mapping of addresses to memory modules with the optimal case. The results are applicable to different multiprocessor architectures, e.g. systems with crossbar networks and systems with multiple buses. The results also make it possible to calculate optimal performance bounds for multiprocessors containing cache memories, as well as for multiprocessors with no cache memories. Moreover, we discuss how the results can be used for calculating bounds for programs with as well as without synchronizations.