Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses
IEEE Transactions on Computers
Efficient synchronization of multiprocessors with shared memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Performance measurements on HEP - a pipelined MIMD computer
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
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A technique for combining produce and consume operations is proposed. An Omega network was designed to work with a pipelined micro multiprocessor system, and each of its nodes to be implemented on a single chip. Without a significant increase in hardware complexity, the nodes combine produce and consume messages in an unbounded way. The combining technique that was developed guarantees that every produce and consume message that is combined will always succeed, adding a new benefit to combining. Results of several simulation runs are presented.