A mathematical model for the transitional region between cache hierarchy levels

Authors:
Michael Krietemeyer;Daniel Versick;Djamshid Tavangarian
Affiliations:
Chair of Computer Architecture, Department of Computer Science, University of Rostock, Rostock, Germany;Chair of Computer Architecture, Department of Computer Science, University of Rostock, Rostock, Germany;Chair of Computer Architecture, Department of Computer Science, University of Rostock, Rostock, Germany
Venue:
IICS'04 Proceedings of the 4th international conference on Innovative Internet Community Systems
Year:
2004

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Abstract

The knowledge of internal structures of the cache-memory hierarchy and its performance is very important in modern computer systems. Therefor, this paper introduces a mathematical model that describes the transition between Level 1 and Level 2 cache of current processors. The theoretical predictions are proved by measurements for two Intel CPUs and an UltraSparc II system.