Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor

  • Authors:
  • V. Milutinovic;M Bettinger;W. Helbig

  • Affiliations:
  • -;-;-

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1989

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Abstract

The authors concentrate on design tradeoffs between the bit-serial multiplier and the full barrel shifter combined with a large register file. They analyze and compare three alternatives for a given set of technology related parameters and a given set of higher level language (HLL) benchmarks. Although their basic concern is the design of a 32-bit GaAs microprocessor on a single chip, the implications of the results are more general.