Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
The cache performance and optimizations of blocked algorithms
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
MemSpy: analyzing memory system bottlenecks in programs
SIGMETRICS '92/PERFORMANCE '92 Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
The influence of caches on the performance of heaps
Journal of Experimental Algorithmics (JEA)
Active memory: a new abstraction for memory system simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The influence of caches on the performance of sorting
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
ACM Computing Surveys (CSUR)
Mtool: An Integrated System for Performance Debugging Shared Memory Multiprocessor Applications
IEEE Transactions on Parallel and Distributed Systems
Gprof: A call graph execution profiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Software methods for improvement of cache performance on supercomputer applications
Software methods for improvement of cache performance on supercomputer applications
Introducing computer systems from a programmer's perspective
Proceedings of the thirty-second SIGCSE technical symposium on Computer Science Education
Writing efficient programs: performance issues in an undergraduate CS curriculum
Proceedings of the 35th SIGCSE technical symposium on Computer science education
The V-Way Cache: Demand Based Associativity via Global Replacement
Proceedings of the 32nd annual international symposium on Computer Architecture
Effective support of simulation in computer architecture instruction
WCAE '02 Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture
Redesigning the string hash table, burst trie, and BST to exploit cache
Journal of Experimental Algorithmics (JEA)
Cache-Conscious collision resolution in string hash tables
SPIRE'05 Proceedings of the 12th international conference on String Processing and Information Retrieval
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The wide-spread use of microprocessor based systems that utilize cache memory to alleviate excessively long DRAM access times introduces a new dimension in the quest to obtain good program performance. To fully exploit the performance potential of these fast processors, programmers must reason about their program's cache performance. Heretofore, this topic has been restricted to the supercomputer, multiprocessor, and academic research community. It is now time to introduce this topic into undergraduate computer science curriculum.As part of the CURIOUS project at Duke University, we are in the initial stages of incorporating cache performance issues into an undergraduate course on software design and implementation. Specifically, we are introducing students to the notion of a cache profile that maps cache behavior to source lines and data structures, and providing a cache profiler that can be used along with other performance debugging tools. In the end, we hope to produce cache conscious programmers that are able to exploit the full performance potential of today's computers.