Strategies for cache and local memory management by global program transformation
Journal of Parallel and Distributed Computing - Special Issue on Languages, Compilers and environments for Parallel Programming
Evaluating Associativity in CPU Caches
IEEE Transactions on Computers
Reducing memory latency via non-blocking and prefetching caches
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Improving data locality with loop transformations
ACM Transactions on Programming Languages and Systems (TOPLAS)
Run-time adaptive cache hierarchy management via reference analysis
Proceedings of the 24th annual international symposium on Computer architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Prefetching Using Markov Predictors
IEEE Transactions on Computers - Special issue on cache memory and related problems
Improving Cache Locality by a Combination of Loop and Data Transformations
IEEE Transactions on Computers - Special issue on cache memory and related problems
Randomized Cache Placement for Eliminating Conflicts
IEEE Transactions on Computers - Special issue on cache memory and related problems
Active Management of Data Caches by Exploiting Reuse Information
IEEE Transactions on Computers
ACM Computing Surveys (CSUR)
Computer Organization and Architecture: Designing for Performance
Computer Organization and Architecture: Designing for Performance
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
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Cache memory has been proved to narrow the latency between CPU and main memory. In this study, an algorithm is presented to improve the cache-hit ratio by using an extension to the locality of references (spatial and temporal). The new algorithm extends the reference flagging to additional data lines already residing in the cache besides the one referenced by the processor. It is an extension to a two-way set associative mapping function working in conjunction with a LRU replacement technique. Experiments conducted with memory access traces of running an electrical circuit simulator showed a slight improvement over the standard LRU technique, justifying the use of the new algorithm.