Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

Authors:
Norman P. Jouppi
Affiliations:
Western Research Laboratory, Digital Equipment Corporation, Palo Alto, CA
Venue:
25 years of the international symposia on Computer architecture (selected papers)
Year:
1998

Evaluating stream buffers as a secondary cache replacement

ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Memory-system design considerations for dynamically-scheduled processors

Proceedings of the 24th annual international symposium on Computer architecture
Cache Memories

ACM Computing Surveys (CSUR)
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?

HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Aspects of cache memory and instruction buffer performance

Aspects of cache memory and instruction buffer performance

CATCH: a mechanism for dynamically detecting Cache-Content-Duplication and its application to instruction caches

Proceedings of the conference on Design, automation and test in Europe
Write activity reduction on flash main memory via smart victim cache

Proceedings of the 20th symposium on Great lakes symposium on VLSI
Data marshaling for multi-core architectures

Proceedings of the 37th annual international symposium on Computer architecture

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