Practical and theoretical considerations on low-power probability-codes for networks-on-chip

  • Authors:
  • Alberto Garcia-Ortiz;Leandro S. Indrusiak

  • Affiliations:
  • Institute for Theoretical Electrical Eng. and Microelectronics, University of Bremen, Bremen, Germany;Dept. of Computer Science, RTS, University of York, York, UK

  • Venue:
  • PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
  • Year:
  • 2010

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Abstract

Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.