A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Energy reduction in VLSI computation modules: an information-theoretic approach
IEEE Transactions on Information Theory
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.