Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
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ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
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In this paper, we propose a robust register-transfer level (RTL) power modeling methodology for functional units. Our models are consistently accurate over a wide range of input statistics, they are automatically constructed and can provide pattern-by-pattern power estimates. An additional desirable feature of our modeling methodology is the capability of accounting for the impact of technology variations, library changes and synthesis tools. Our methodology is based on the concept of node sampling, as opposed to more traditional approaches based on input sampling.