Architectural synthesis of flow-based microfluidic large-scale integration biochips

  • Authors:
  • Wajid Hassan Minhass;Paul Pop;Jan Madsen;Felician Stefan Blaga

  • Affiliations:
  • Technical University of Denmark, Kongens Lyngby, Denmark;Technical University of Denmark, Kongens Lyngby, Denmark;Technical University of Denmark, Kongens Lyngby, Denmark;Technical University of Denmark, Kongens Lyngby, Denmark

  • Venue:
  • Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
  • Year:
  • 2012

Quantified Score

Hi-index 0.00

Visualization

Abstract

Microfluidic biochips are replacing the conventional biochemical analyzers and are able to integrate the necessary functions for biochemical analysis on-chip. In this paper we are interested in flow-based biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex units, such as micropumps, switches, mixers, and multiplexers, can be built. The manufacturing technology, soft lithography, used for the flow-based biochips is advancing faster than Moore's law, resulting in increased architectural complexity. However, the designers are still using full-custom and bottom-up, manual techniques in order to design and implement these chips. As the chips become larger and the applications become more complex, the manual methodologies will not scale, becoming highly inadequate. Therefore, for the first time to our knowledge,we propose a top-down architectural synthesis methodology for the flow-based biochips. Starting from a given biochemical application and a microfluidic component library, we are interested in synthesizing a biochip architecture, i.e., performing component allocation from the library based on the biochemical application, generating the biochip schematic (netlist) and then performing physical synthesis (deciding the placement of the microfluidic components on the chip and performing routing of the microfluidic channels), such that the application completion time is minimized. We evaluate our proposed approach by synthesizing architectures for real-life applications as well as synthetic benchmarks.