Advanced compiler design and implementation
Advanced compiler design and implementation
A 50 Mbit/s iterative turbo-decoder
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Dynamic common sub-expression elimination during scheduling in high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
Efficient factorization of DSP transforms using taylor expansion diagrams
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Data-flow transformations using Taylor expansion diagrams
Proceedings of the conference on Design, automation and test in Europe
Practical fpga programming in c
Practical fpga programming in c
High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
Special Issue on High-Level Synthesis
IEEE Design & Test
Optimizing data flow graphs to minimize hardware implementation
Proceedings of the Conference on Design, Automation and Test in Europe
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During Electronic System-Level (ESL) design, High-Level Synthesis (HLS) tools normally translate the system description to a Control/Data Flow Graph. At this level, several transformations are performed as early as possible to reduce the number and complexity of the data operations. These preliminary transformations (for example, common sub-expression elimination, constant propagation, etc) are typically applied in algebraic expressions with arithmetic operators. This paper presents preliminary transformations that optimize Data-Flow Graphs with relational, maximum/minimum and arithmetic (addition/subtraction) operations. The proposed techniques produce a significant reduction in the number of operations. HLS tools and even software compilers and symbolic algebra packages are not able to generate similar results. The efficiency of the techniques has been evaluated with several modules of real telecommunications standards and their HW implementations show important area reductions and, sometimes, low impact on latency or critical path.