Communication on the Fly for Hierarchical Systems of Chip Multi-processors

Authors:
Marek Tudruj;Lukasz Masko
Affiliations:
-;-
Venue:
PARELEC '11 Proceedings of the 2011 Sixth International Symposium on Parallel Computing in Electrical Engineering
Year:
2011

Citing 0
Cited 3

Communication and memory architecture design of application-specific high-end multiprocessors

VLSI Design
Scalable communication architectures for massively parallel hardware multi-processors

Journal of Parallel and Distributed Computing
Design of massively parallel hardware multi-processors for highly-demanding embedded applications

Microprocessors & Microsystems

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Abstract

Systems based on many Chip Multi-Processor (CMP) modules interconnected by global networks constitute now a feasible solution, which brings back to life challenges of massively parallel systems. The paper presents new methods for data communication inside CMP modules and for inter-CMP-module data communication. Inside CMP modules data communication through shared variables is improved by the use of dynamic core switching between core clusters organized in a system of multi-level caches with data reads on the fly. At the level of global data communication between CMP modules a special network implements communication between CMP module external shared memories with simultaneous reads on the fly to L2 data caches and main memories of CMP modules. Programs are built following a macro data flow graph paradigm.