REYSM, a high performance, low power multi-processor bus

Authors:
J. D. Nicoud;K. Skala
Affiliations:
Swiss Federal Institute of Technology, Av, de Cour 37, CH-1007 Lausanne;Swiss Federal Institute of Technology, Av, de Cour 37, CH-1007 Lausanne
Venue:
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Year:
1986

Citing 4
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Abstract

In order to build lower cost multimicroprocessor systems, a narrow synchronous bus (15 active lines) is proposed. It multiplexes address and data on 8 bits, and arbitrates in two pipe-lined cycles on four lines. Due to the 20 to 40 MHz bus clock, and the pipelined control logic, the performances are equivalent to Multibus-2, IEEE-P896 and similar 32-bit buses.For the implementation, cards are disposed radially around a special connector. The very short connections allows for the usage of fast HC-MOS drivers with only a light adaptation.