Optimal checkpointing of real-time tasks
IEEE Transactions on Computers
An On-Line Algorithm for Checkpoint Placement
IEEE Transactions on Computers
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
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Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Performance optimization for energy-aware adaptive checkpointing in embedded real-time systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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ACM Transactions on Embedded Computing Systems (TECS)
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Proceedings of the 48th Design Automation Conference
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UIC'11 Proceedings of the 8th international conference on Ubiquitous intelligence and computing
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EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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EDCC'05 Proceedings of the 5th European conference on Dependable Computing
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The Journal of Supercomputing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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We present an integrated approach that provides fault tolerance and dynamic power management for a real-time task executing in an embedded system. Fault tolerance is achieved through an adaptive checkpointing scheme that dynamically adjusts the checkpointing interval during task execution. Adaptive checkpointing is then combined with a dynamic voltage scaling scheme to achieve power reduction. The resulting energy-aware adaptive checkpointing scheme uses a dynamic voltage scaling criterion that is based not only on the slack in task execution but also on the occurrences of faults during task execution. Simulation results show that compared to previous methods, the proposed approach significantly reduces power consumption and increases the likelihood of timely task completion in the presence of faults.