Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Managing Power Consumption in Networks on Chip
Proceedings of the conference on Design, automation and test in Europe
Power-aware communication optimization for networks-on-chips with voltage scalable links
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Peak Power Control for a QoS Capable On-Chip Network
ICPP '05 Proceedings of the 2005 International Conference on Parallel Processing
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Adaptive Power Management for the On-Chip Communication Network
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
A Process Scheduler-Based Approach to NoC Power Management
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
SAPP: scalable and adaptable peak power management in nocs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Ant system: optimization by a colony of cooperating agents
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
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In Network-on-Chip (NoC) based complex system design on-chip power management is a challenging issue. Most power management schemes fail to provide optimal power sharing among on-chip routers when the power budget distribution varies significantly due to their non-uniform placement on chip. This paper presents PowerAntz, an ant system inspired distributed power management strategy for NoC based systems. This is an adaptive and distributed approach to power sharing across routers of a large network on chip and it is shown to be a scalable solution. A detailed flit accurate simulator was developed in SystemC to evaluate the efficiency of the technique. The experiments demonstrate PowerAntz to be up to 30% more effective in distributing power budget compared to existing strategies. Further, it also achieves up to 21.25% improvement in power budget utilization while keeping the energy overhead negligible for best case scenarios.