Proceedings of the 6th international workshop on Hardware/software codesign
Embedded system synthesis under memory constraints
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The Niched Pareto Genetic Algorithm 2 Applied to the Design of Groundwater Remediation Systems
EMO '01 Proceedings of the First International Conference on Evolutionary Multi-Criterion Optimization
Application partitioning on programmable platforms using the ant colony optimization
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
The Challenges of Embedded System Design
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Dominance-Based Multiobjective Simulated Annealing
IEEE Transactions on Evolutionary Computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architecture-driven reliability optimization with uncertain model parameters
Journal of Systems and Software
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In this paper, we apply multi-objective evolutionary computation to the synthesis of real-time, embedded, heterogeneous, multiprocessor systems (briefly, Multiprocessor Systems-on-Chip or MP-SoCs). Our approach simultaneously explores the architecture, the mapping and the scheduling of the system, by using multi-objective evolution. In particular, we considered three approaches: a multi-objective genetic algorithm, multi-objective Simulated Annealing, and multi-objective Tabu Search. The algorithms search for optimal architectures, in terms of processing elements (processors and hardware accelerators) and communication infrastructure, and for the best mappings and schedules of multi-rate real-time applications given objectives such as: system area, hard and soft dead-lines violations, dimensions of memory buffers. We formalize the problem, describe our flow and compare the three algorithms, dis- cussing which one performs better with respect to different classes of applications.