Colif: A Design Representation for Application-Specific Multiprocessor SOCs
IEEE Design & Test
Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels
RSP '07 Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using UML as front-end for heterogeneous software code generation strategies
Proceedings of the conference on Design, automation and test in Europe
Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors
Journal of Signal Processing Systems
Integration, the VLSI Journal
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
SysCOLA: a framework for co-development of automotive software and system platform
Proceedings of the 46th Annual Design Automation Conference
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient high-level modeling in the networking domain
Proceedings of the Conference on Design, Automation and Test in Europe
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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System-level design methodologies have been introduced as a solution to handle the design complexity of embedded multiprocessor SoC (MPSoC) systems. In this paper we describe a system-level design flow starting from Simulink specification, focusing on concurrent hardware and software design and verification at four different abstraction levels: Simulink Combined Algorithm and Architecture Model (CAAM), Virtual Architecture, Transaction-accurate Model and Virtual Prototype. We used two multimedia applications, Motion-JPEG and H.264, to evaluate this design flow. Experimental results show that our design flow can generate various MPSoC architectures from Simulink CAAM correctly and efficiently, allowing processor and task design space exploration at different abstraction levels.