The program structure tree: computing control regions in linear time
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
A framework for evaluating design tradeoffs in packet processing architectures
Proceedings of the 39th annual Design Automation Conference
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Compilation-based software performance estimation for system level design
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling
Proceedings of the 30th annual international symposium on Computer architecture
AWorkload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors
HICSS '97 Proceedings of the 30th Hawaii International Conference on System Sciences: Software Technology and Architecture - Volume 1
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Guest Editors' Introduction: The True State of the Art of ESL Design
IEEE Design & Test
HySim: a fast simulation framework for embedded software development
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
MAPS: an integrated framework for MPSoC application parallelization
Proceedings of the 45th annual Design Automation Conference
Source-level timing annotation and simulation for a heterogeneous multiprocessor
Proceedings of the conference on Design, automation and test in Europe
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate source-level simulation of embedded software with respect to compiler optimizations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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While Multiprocessor System-On-Chips (MPSoCs) are becoming widely adopted in embedded systems, there is a strong need for methodologies that quickly and accurately estimate performance of such complex systems. In this paper, we present a novel method for accurately estimating the cycle counts of parameterized MPSoC architectures through workload simulation driven by program execution traces encoded in the form of branch bitstreams. Experimental results show that the proposed method delivers a speedup factor of 70.15 to 238.58 against the instruction-set simulator based method while achieving high cycle accuracy whose estimation error ranges between 0.016% and 0.459%.