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ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Debugging HW/SW interface for MPSoC: video encoder system design case study
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Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
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HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC
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Trace-driven workload simulation method for Multiprocessor System-On-Chips
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EURASIP Journal on Embedded Systems
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This paper presents a Multiprocessor System-on-Chips (MPSoC) architecture used as an execution platform for the new C-language based MPSoC design framework we are currently developing. The MPSoC architecture is based on an existing SoC platform with a commercial RISC core acting as the host CPU. We extend the existing SoC with a multiprocessor-array block that is used as the main engine to run parallel applications modeled in our design framework. Utilizing several optimizations provided by our compiler, an efficient inter-communication between processing elements with minimum overhead is implemented. A host-interface is designed to integrate the existing RISC core to the multiprocessor-array. The experimental results show that an efficacious integration is achieved, proving that the designed communication module can be used to efficiently incorporate off-the-shelf processors as a processing element for MPSoC architectures designed using our framework.