HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems

Authors:
Nicolas Saint-Jean;Gilles Sassatelli;Pascal Benoit;Lionel Torres;Michel Robert
Affiliations:
LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France;LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France;LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France;LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France;LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France
Venue:
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Year:
2007

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Abstract

Scalability of architecture, programming model and task control management will be a major challenge for MP-SOC designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-SOC. Our architecture, H-Scale, is a homogeneous MP-SOC based on RISC processors, distributed memories and an asynchronous network on chip. S-Scale is a multi-threaded sequential programming model with dedicated communication primitives handled at run-time by a simple Operating System we developed. The hardware validations and experiments on applications such as MJPEG and FIR filters demonstrate the scalability of our approach and draws interesting perspectives for distributed strategies of task control management.