Automatic Generation of Simulation Monitors from Quantitative Constraint Formula

Authors:
Xi Chen;Harry Hsieh;Felice Balarin;Yosinori Watanabe
Affiliations:
University of California at Riverside;University of California at Riverside;Cadence Berkeley Laboratories;Cadence Berkeley Laboratories
Venue:
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2003

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Abstract

System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulation will remain an important tool for making sure that implementations perform as they should. In this paper we present algorithms to automatically generate C++ checkers from any formula written in the formal quantitative constraint language, Logic Of Constraints (LOC). The executable can then be used to analyze the simulation traces for constraint violation and output debugging information. Different checkers can be generated for fast analysis under different memory limitations. LOC is particularly suitable for specification of system level quantitative constraints where relative coordination of instances of events, not lower level interaction, is of paramount concern. We illustrate the usefulness and efficiency of our automatic trace analysis methodology with case studies on large simulation traces from various system level designs.