Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions

Authors:
Sudarshan K. Srinivasan;Miroslav N. Velev
Affiliations:
-;-
Venue:
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Year:
2003

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Abstract

We present the formal verification of an Intel Xscale processor model.The Xscale is a superpipelined RISC processor with 7-stage integer, 8-stage memory, and variable-latency multiply-and-accumulate execution pipelines.The processor uses scoreboarding to track data dependencies, and implements both precise and imprecise exceptions.Such set of features had not been modeled, and formally verified previously.The formal verification was done with an automatic toll flow that consists of the term-level symbolic simulator TLSim, the decision procedure EVC, and an efficient SAT-checker.