An MDE-based approach to the verification of SysML state machine diagram
Proceedings of the Fourth Asia-Pacific Symposium on Internetware
| Hi-index | 0.00 |
The modeling, simulation and verification of real-time systems can be unified and the efficiency of system development can be improved if the UML timing diagram model can be translated into the timed automata model. The conversion rules and the algorithm are given in this paper. A coffee machine control system is given as an example in which we give the UML timing diagram model and translate it to timed automata model in UPPAAL, then we verify the accessibility, the security and the activity of the system by UPPAAL.