The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Parametric real-time reasoning
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
Theoretical Computer Science
Model-based testing in practice
Proceedings of the 21st international conference on Software engineering
Distributed Algorithms
ICALP '92 Proceedings of the 19th International Colloquium on Automata, Languages and Programming
Linear Parametric Model Checking of Timed Automata
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
On Discretization of Delays in Timed Automata and Digital Circuits
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
Time-Constrained Automata (Extended Abstract)
CONCUR '91 Proceedings of the 2nd International Conference on Concurrency Theory
Automating the Generation and Sequencing of Test Cases from Model-Based Specifications
FME '93 Proceedings of the First International Symposium of Formal Methods Europe on Industrial-Strength Formal Methods
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Parametric real-time model checking using splitting trees
Nordic Journal of Computing
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Revisiting Digitization, Robustness, and Decidability for Timed Automata
LICS '03 Proceedings of the 18th Annual IEEE Symposium on Logic in Computer Science
Formal modeling and analysis of an audio/video protocol: an industrial case study using UPPAAL
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Hardware timing verification using KRONOS
ICCSSE '96 Proceedings of the 7th Israeli Conference on Computer-Based Systems and Software Engineering
The Generalized Railroad Crossing: A Case Study in Formal Verification of Real-Time Systems
The Generalized Railroad Crossing: A Case Study in Formal Verification of Real-Time Systems
Symbolic Parametric Safety Analysis of Linear Hybrid Systems with BDD-Like Data-Structures
IEEE Transactions on Software Engineering
Fast On-the-Fly Parametric Real-Time Model Checking
RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
Analysis of a biphase mark protocol with Uppaal and PVS
Formal Aspects of Computing
The Theory of Timed I/O Automata (Synthesis Lectures in Computer Science)
The Theory of Timed I/O Automata (Synthesis Lectures in Computer Science)
Machine-Assisted Parameter Synthesis of the Biphase Mark Protocol Using Event Order Abstraction
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Analysis of a clock synchronization protocol for wireless sensor networks
Theoretical Computer Science
Model checking of hybrid systems using shallow synchronization
FMOODS'10/FORTE'10 Proceedings of the 12th IFIP WG 6.1 international conference and 30th IFIP WG 6.1 international conference on Formal Techniques for Distributed Systems
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We present a new abstraction technique, event order abstraction} (EOA), for parametric safety verification of real-time systems in which "correct orderings of events" needed for system correctness are maintained by timing constraints on the systems' behavior. By using EOA, one can separate the task of verifying a real-time system into two parts: 1. Safety property verification of the system given that only correct event orderings occur; and 2. Derivation of timing parameter constraints for correct orderings of events in the system. The user first identifies a candidate set of bad event orders. Then, by using ordinary untimed model-checking, the user examines whether a discretized system model in which all timing constraints are abstracted away satisfies a desirable safety property under the assumption that the identified bad event orders occur in no system execution. The user uses counterexamples obtained from the model-checker to identify additional bad event orders, and repeats the process until the model-checking succeeds. In this step, the user obtains a sufficient set of bad event orders that must be excluded by timing synthesis for system correctness. Next, the algorithm presented in the paper automatically derives a set of timing parameter constraints under which the system does not exhibit the identified bad event orderings. From this step combined with the untimed model-checking step, the user obtains a sufficient set of timing parameter constraints under which the system executes correctly with respect to a given safety property. We illustrate the use of EOA with a train-gate example inspired by the general railroad crossing problem [13]. We also summarize three other case studies, a biphase mark protocol, the IEEE 1394 root contention protocol, and the Fischer mutual exclusion algorithm.