Event order abstraction for parametric real-time system verification
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
A Compositional Translation of Timed Automata with Deadlines to Uppaal Timed Automata
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Machine-Assisted Parameter Synthesis of the Biphase Mark Protocol Using Event Order Abstraction
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Model checking the FlexRay physical layer protocol
FMICS'10 Proceedings of the 15th international conference on Formal methods for industrial critical systems
Formal specification and analysis of zeroconf using uppaalS
ACM Transactions on Embedded Computing Systems (TECS)
Analysis of a clock synchronization protocol for wireless sensor networks
Theoretical Computer Science
FORMATS'12 Proceedings of the 10th international conference on Formal Modeling and Analysis of Timed Systems
Analyzing an embedded sensor with timed automata in uppaal
ACM Transactions on Embedded Computing Systems (TECS)
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The biphase mark protocol is a convention for representing both a string of bits and clock edges in a square wave. The protocol is frequently used for communication at the physical level of the ISO/OSI hierarchy, and is implemented on microcontrollers such as the Intel 82530 Serial Communications Controller. An important property of the protocol is that bit strings of arbitrary length can be transmitted reliably, despite differences in the clock rates of sender and receiver (drift), variations of the clock rates (jitter), and distortion of the signal after generation of an edge. In this article, we show how the protocol can be modelled naturally in terms of timed automata. We use the model checker Uppaal to derive the maximal tolerances on the clock rates, for different instances of the protocol, and to support the general parametric verification that we formalized using the proof assistant PVS. Based on the derived parameter constraints we propose instances of BMP that are correct (at least in our model) but have a faster bit rate than the instances that are commonly implemented in hardware.