Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Communication and concurrency
Timing assumptions and verification of finite-state concurrent systems
Proceedings of the international workshop on Automatic verification methods for finite state systems
Minimal state graph generation
Science of Computer Programming
Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
The algorithmic analysis of hybrid systems
Theoretical Computer Science - Special issue on hybrid systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Symbolic Model Checking
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
Probabilistic simulations for probabilistic processes
Nordic Journal of Computing
Minimization of Timed Transition Systems
CONCUR '92 Proceedings of the Third International Conference on Concurrency Theory
A Space-Efficient On-the-fly Algorithm for Real-Time Model Checking
CONCUR '96 Proceedings of the 7th International Conference on Concurrency Theory
Partition Refinement in Real-Time Model Checking
FTRTFT '98 Proceedings of the 5th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
An Efficient Algorithm for Minimizing Real-time Transition Systems
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Local Model Checking for Real-Time Systems (Extended Abstract)
Proceedings of the 7th International Conference on Computer Aided Verification
Algorithmic Analysis of Nonlinear Hybrid Systems
Proceedings of the 7th International Conference on Computer Aided Verification
Analysis of Timed Systems Based on Time-Abstracting Bisimulation
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Lectures on Embedded Systems, European Educational Forum, School on Embedded Systems
Model-Checking for Real-Time Systems
FCT '95 Proceedings of the 10th International Symposium on Fundamentals of Computation Theory
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Application of Parametric Model Checking - The Root Contention Protocol
HICSS '01 Proceedings of the 34th Annual Hawaii International Conference on System Sciences ( HICSS-34)-Volume 9 - Volume 9
Parametric verification of the IEEE 1394a Root Contention protocol using LPMC
RTCSA '00 Proceedings of the Seventh International Conference on Real-Time Systems and Applications
Compositional and symbolic model-checking of real-time systems
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Description and formal specification of the Link Layer of P1394
Description and formal specification of the Link Layer of P1394
Parametric Analysis of Real-Time Embedded Systems with Abstract Approximation Interpretation
Proceedings of the 26th International Conference on Software Engineering
Event order abstraction for parametric real-time system verification
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Machine-Assisted Parameter Synthesis of the Biphase Mark Protocol Using Event Order Abstraction
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
Predicate Diagrams for the Verification of Real-Time Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Efficient model-checking of dense-time systems with time-convexity analysis
Theoretical Computer Science
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This article discusses a new approach to model checking of real-time systems. One of the novel aspects of our approach is the fact that an unconventional approach is chosen to deal with representing symbolic state spaces. Its key feature is that it does not use a canonical representation for representing symbolic nodes, but an alternative representation based on splitting trees. We describe this approach in terms of the verification problem of parametric reacheability of systems described in an extension of timed automata. Additionally, we describe how we extended this approach to deal With more complex verification problems, namely the parametric verification of an extension of the real-time temporal logic TCTL. This resulted in a model checking tool called PMC. The practical application of our approach is addressed through the analysis and verification of the root contention protocol of the IEEE1394 (FireWire) standard using this tool.