Partial Order Reductions for Timed Systems
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Bounded LTL model checking with stable models
Theory and Practice of Logic Programming
Symbolic Parametric Safety Analysis of Linear Hybrid Systems with BDD-Like Data-Structures
IEEE Transactions on Software Engineering
Predicate abstraction for reachability analysis of hybrid systems
ACM Transactions on Embedded Computing Systems (TECS)
HySAT: An efficient proof engine for bounded model checking of hybrid systems
Formal Methods in System Design
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Event order abstraction for parametric real-time system verification
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Verifying Industrial Hybrid Systems with MathSAT
Electronic Notes in Theoretical Computer Science (ENTCS)
Efficient Proof Engines for Bounded Model Checking of Hybrid Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Reachability for linear hybrid automata using iterative relaxation abstraction
HSCC'07 Proceedings of the 10th international conference on Hybrid systems: computation and control
Peephole partial order reduction
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
BACH 2: Bounded reachAbility CHecker for compositional linear hybrid systems
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient scenario verification for hybrid automata
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Proving and explaining the unfeasibility of message sequence charts for hybrid systems
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
SMT-based scenario verification for hybrid systems
Formal Methods in System Design
| Hi-index | 0.00 |
Hybrid automata are a widely accepted modeling framework for systems with discrete and continuous variables. The traditional semantics of a network of automata is based on interleaving, and requires the construction of a monolithic hybrid automaton based on the composition of the automata. This destroys the structure of the network and results in a loss of efficiency, especially using bounded model checking techniques. An alternative compositional semantics, called “shallow synchronization”, exploits the locality of transitions and relaxes time synchronization. The semantics is obtained by composing traces of the local automata, and superimposing compatibility constraints resulting from synchronization. In this paper, we investigate the different symbolic encodings of the reachability problem of a network of hybrid automata. We propose a novel encoding based on the shallow synchronization semantics, which allows different strategies for searching local paths that can be synchronized. We implemented a bounded reachability search based on the use of an incremental Satisfiability-Modulo-Theory solver. The experimental results confirm that the new encoding often performs better than the one based on interleaving.