Verifying Stateful Timed CSP Using Implicit Clocks and Zone Abstraction
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Journal of Systems and Software
Layered composition for timed automata
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
A framework for relating timed transition systems and preserving TCTL model checking
EPEW'10 Proceedings of the 7th European performance engineering conference on Computer performance engineering
Verification of timed-arc Petri nets
SOFSEM'11 Proceedings of the 37th international conference on Current trends in theory and practice of computer science
Validating time-constrained systems using UML statecharts patterns and timed automata observers
VECoS'09 Proceedings of the Third international conference on Verification and Evaluation of Computer and Communication Systems
Automatic verification of real-time systems with rich data: an overview
TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
Revising and extending the uppaal communication mechanism
SC'12 Proceedings of the 11th international conference on Software Composition
Modeling and verifying hierarchical real-time systems using stateful timed CSP
ACM Transactions on Software Engineering and Methodology (TOSEM)
ACM Computing Surveys (CSUR)
PSyHCoS: parameter synthesis for hierarchical concurrent real-time systems
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Modelling temporal behaviour in complex systems with Timebands
Formal Methods in System Design
A formal framework to specify and verify real-time properties on critical systems
International Journal of Critical Computer-Based Systems
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Timed Automata have proven to be useful for specification and verification of real-time systems. System design using Timed Automata relies on explicit manipulation of clock variables. A number of automated analyzers for Timed Automata have been developed. However, Timed Automata lack of composable patterns for high-level system design. Logic-based specification languages like Timed CSP and TCOZ are well suited for presenting compositional models of complex real-time systems. In this work, we define a set of composable Timed Automata patterns based on hierarchical constructs in timed enriched process algebras. The patterns facilitate hierarchical design of complex systems using Timed Automata. They also allow a systematic translation from Timed CSP/TCOZ models to Timed Automata so that analyzers for Timed Automata can be used to reason about TCOZ models. A prototype has been developed to support system design using Timed Automata patterns or, if given a TCOZ specification, to automate the translation from TCOZ to Timed Automata.