Timing assumptions and verification of finite-state concurrent systems
Proceedings of the international workshop on Automatic verification methods for finite state systems
Modeling and Verification of Time Dependent Systems Using Time Petri Nets
IEEE Transactions on Software Engineering
Algorithms for synthesis of hazard-free asynchronous circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Representing and modeling digital circuits
Representing and modeling digital circuits
Using Partial Orders to Improve Automatic Verification Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Stubborn sets for reduced state space generation
Proceedings of the 10th International Conference on Applications and Theory of Petri Nets: Advances in Petri Nets 1990
Efficient Timing Analysis of a Class of Petri Nets
Proceedings of the 7th International Conference on Computer Aided Verification
Synthesis of Asynchronous Controllers for Heterogeneous Systems
Synthesis of Asynchronous Controllers for Heterogeneous Systems
Automatic Synthesis and Verification of Gate-Level Timed Circuits
Automatic Synthesis and Verification of Gate-Level Timed Circuits
Efficient verification using generalized partial order analysis
Proceedings of the conference on Design, automation and test in Europe
Timed Verification of Asynchronous Circuits
Concurrency and Hardware Design, Advances in Petri Nets
CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic
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