Performance analysis of data-driven networks
Systolic array processors
Performance analysis and optimization of asynchronous circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Co-synthesis of hardware and software for digital embedded systems
Co-synthesis of hardware and software for digital embedded systems
Scheduling Parallel Computations
Journal of the ACM (JACM)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
A framework for interactive analysis of timing constraints in embedded systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Rate Analysis for Embedded Systems
Rate Analysis for Embedded Systems
Specification and analysis of timing constraints for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Embedded systems consist of interacting components that are required to deliver a specific functionality under constraints on execution rated and relative time separation of the components. In this article, we model an embedded system using concurrent processes interacting through synchronization. We assume that there are rate constraints on the execution rates of processes imposed by the designer or the environment of the system, where the execution rate of a process is the number of its executions per unit time. We address the problem of computing bounds on the execution rates of processes constituting an embedded system, and propose an interactive rate analysis framework. As part of the rate analysis framework we present an efficient algorithm for checking the consistency of the rate constraints. Bounds on the execution rate of each process are computed using an efficient algorithm based on the relationship between the execution rate of a process and the maximum mean delay cycles in the process graph. Finally, if the computed rates violate some of the rate constraints, some of the processes in the system are redesigned using information from the rate analysis step. This rate analysis framework is implemented in a tool called RATAN. We illustrate by an example how RATAN can be used in an embedded system design.