High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Rate Analysis for Embedded Systems
Rate Analysis for Embedded Systems
Specification and analysis of timing constraints for embedded systems
Specification and analysis of timing constraints for embedded systems
Multiprocessors, semaphores, and a graph model of computation
Multiprocessors, semaphores, and a graph model of computation
Rate analysis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Rate analysis for embedded systems
Readings in hardware/software co-design
Multi-thread graph: a system model for real-time embedded software synthesis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Software Implementation Techniques for Hw/Sw Embedded Systems
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Computing communication cost by Petri nets for hardware/software codesign
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
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An important goal of embedded system co-synthesis is to realize system designs under constraints on timing performance. We present applicable constraints and the notion of satisfiability of a given set of constraints. We describe a two-level system model that is useful for carrying out constraint analysis in presence of the timing and execution uncertainty inherent in embedded systems. We conclude by presenting a framework to determine constraint satisfiability and to interactively debug constraint violations. Examples are presented to show the utility of our approach.