Analysis of operation delay and execution rate constraints for embedded systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A framework for interactive analysis of timing constraints in embedded systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
| Hi-index | 0.00 |
Embedded systems consist of interacting components that are required to deliver a specific functionality under constraints on execution rates and relative timing of the components. In this paper we study the problem of computing bounds on the execution rates of the various components of an embedded system that is modeled by concurrent processes interacting through synchronization. We use an algebraic model in (max,+) algebra to capture the timing semanics of the process level synchronization and show the relation between eigenvalues of the process adjacency matrix and average process execution rates. An efficient algorithm is presented for computing process execution rates and using them to compute execution rates for operations within processes. Our algorithms for rate analysis can handle pipelined processes that can be re-invoked before a previous instance has terminated. We present an interactive framework for debugging rate constaint violations using our rate analysis algorithms. The proposed algorithms are implemented in a tool, \fIRatan\fR. We illustrate by examples how \fIRatan\fR can be used in embedded system design.