Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A co-synthesis approach to embedded system design automation
Design Automation for Embedded Systems
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Specification and analysis of timing constraints for embedded systems
Specification and analysis of timing constraints for embedded systems
Multiprocessors, semaphores, and a graph model of computation
Multiprocessors, semaphores, and a graph model of computation
Performance Analysis for a Java-based Virtual Prototype
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
| Hi-index | 0.00 |