Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Low-power and low-voltage CMOS digital design
Proceedings of the first session on Low-power, low-voltage integrated circuits : technology and design: technology and design
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A novel methodology and algorithm for the design of large low-power asynchronous systems are described. The system is synthesized by a commercial tool as a synchronous circuit, and subsequently converted into an asynchronous one. The conversion algorithm consists ofextracting input and output sets, replacing the storage elements, identifying fork and join sets, and constructing request and acknowledge networks. A DLAP (Doubly Latched Asynchronous Pipeline) architecture is employed. The resulting asynchronous circuit can adapt its effective operating frequency to the supply voltage, facilitating flexible and efficient power management. The algorithm has been validated on several circuits.