Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
| Hi-index | 0.00 |
As the feature size offered by VLSI technology shrinks,circuit performance as well as circuit complexity increases.This puts considerable pressure on the synchronousdesign methodology, mainly due to the difficultyof routing a low skew high frequency clocks signalacross a large die.On the other hand, the synchronousdesign methodology offers the benefits of amature design flow and a comprehensive set of designtools.In this paper, we present an approach towards theelimination of the global clock signal in a synchronousdesign.We present a novel partitioning strategy andthe design of a distributed asynchronous controller forthis purpose.The transformed circuit can have performancecomparable or possibly superior to the originalsynchronous circuit (provided clock could be distributedin the first place).The technique is demonstrated by apilot design in a .18 micron TSMC process, and is agood candidate for a clock-less design methodology builtaround the principle of desynchronization.